The present invention addresses the increasing proportion of integrated circuit testing costs relative to the integrated circuit fabrication costs. For example, thousands of integrated circuits can be fabricated at the same time on a single silicon wafer. However, each integrated circuit generally has to be tested serially (e.g., one at a time). Such serial operations are fundamentally more expensive than parallel operations. The industry has responded to this problem by (1) manufacturing more transistors and functionality onto each integrated circuit in order to amortize the testing cost over a larger number of transistors, (2) incorporating self-testing capability into the individual integrated circuits, and/or (3) testing multiple integrated circuits at the same time by mechanically probing multiple neighboring clusters of integrated circuits with complex probe card assemblies and hundreds of probe pads.
However, each of these solutions has disadvantages. First, many modern electronic systems (e.g., RFID tags, smart cards, or other embedded computer systems) require billions and perhaps even trillions of low-cost integrated circuits. Thus, it may be ineffective to increase the number of transistors and the functionality on each integrated circuit. Second, although integrated circuits may be able to self-test, individual mechanical test probes may still be required to provide necessary power and timing signals. This continues to limit the speed at which small integrated circuits can be tested. In addition, mechanical inking is also still necessary to identify integrated circuits that failed testing so that functional integrated circuits can be sorted after the scribe and dice operation. Third, the process of testing multiple neighboring clusters of integrated circuits using complex probe card assemblies having hundreds of probe pads dramatically increases the cost of the probe card, and also increases the likelihood of a probe malfunction. Furthermore, the number of integrated circuits in the cluster may be limited because simultaneous mechanical contact with each pad within the cluster is required. In turn, this limits the throughput increase to a value in the range of from 2× to 10×. Thus, need is felt for improved reliability of the integrated circuit testing process without increasing the testing costs, or preferably, while decreasing the costs of testing.